Patents in suit

US 10,903,734 Delivering power to semiconductor loads

3 defendants · 6 suits · updated October 6, 2026

Also cited as U.S. Patent No. 10,903,734 · US10903734B1 · US 10,903,734 B1 · 10903734 · the '734 patent

Vicor Corporation has filed 6 patent-infringement suits on US 10,903,734, "Delivering power to semiconductor loads" since September 8, 2026, 4 of them in the W.D. Tex., against 3 distinct defendants including Chengdu Monolithic Power Systems Co., Ltd., Delta Electronics (Americas) Ltd. and Flex Ltd.. The patent is held by Vicor Corp and was granted January 26, 2021 on a priority date of April 5, 2016. Its abstract opens: "Encapsulated electronic modules having complex contact structures may be formed by encapsulating panels containing a substrate comprising pluralities of electronic modules delineated by cut lines and having conductive interconnects buried within terminal…" The examiner cited 1 reference during prosecution.

Assignee
Vicor Corp
Priority date
April 5, 2016
Granted
January 26, 2021
Expires
April 5, 2036
Status
Active
Claims
113 (11 independent)
Inventors
Patrizio Vinciarelli
Full text
Google Patents

The suits

6 cases · W.D. Tex. (4) · E.D. Tex. (2)

Filed Defendant Plaintiff Court Docket
2026-09-08 Chengdu Monolithic Power Systems Co., Ltd. Vicor Corporation W.D. Tex. 7:26-cv-00364
2026-09-08 Chengdu Monolithic Power Systems Co., Ltd. Vicor Corporation W.D. Tex. 7:26-cv-00364
2026-09-08 Delta Electronics (Americas) Ltd. Vicor Corporation E.D. Tex. 2:26-cv-00796
2026-09-08 Delta Electronics (Americas) Ltd. Vicor Corporation E.D. Tex. 2:26-cv-00796
2026-09-08 Flex Ltd. Vicor Corporation W.D. Tex. 7:26-cv-00365
2026-09-08 Flex Ltd. Vicor Corporation W.D. Tex. 7:26-cv-00365

Docket links open the public record on CourtListener. Filing dates are the complaint's.

Independent claims

What is actually asserted, verbatim.

Claim 1

1. A method of powering a semiconductor device having power input terminals, the method comprising: providing a power conversion module having conversion circuitry arranged in a multi-cell structure having a plurality of conversion cells, each conversion cell including one or more converter output terminals, the conversion circuitry being configured to convert power received at a first voltage for delivery via the converter output terminals of the plurality of conversion cells at a second lower voltage, the converter output terminals being arranged in a first pattern having a first spacing between the converter output terminals; providing an interconnection module having x-input terminals arranged on a first side of the interconnection module in a pattern configured to align with the first pattern of converter output terminals, and x-output terminals arranged on a surface of a second opposite side of the interconnection module in a second pattern configured to align with the power input terminals of the semiconductor device, the second pattern having a second spacing between x-output terminals, the second spacing being different than the first spacing, the x-input terminals being electrically connected to the x-output terminals; assembling the power conversion module to the first side of the interconnection module with each converter output terminal mated with and electrically connected to a respective x-input terminal; wherein the interconnection module is configured to provide electrical and mechanical translation between the converter output terminals arranged in the first pattern and the power input terminals of the semiconductor device arranged in the second pattern; wherein the power conversion module and the interconnection module are stacked to form a module sandwich including the power conversion module in a first layer, electrical connections between the converter output terminals and the x-input terminals in a second layer, and the interconnection module in a third layer.

Claim 2

2. A method of powering a semiconductor device, including at least one semiconductor die having a plurality of die power input terminals arranged on a surface of the die and having edges of the semiconductor die defining a die footprint, the semiconductor device having power input terminals arranged within the footprint of the die, the method comprising: providing a power conversion module having conversion circuitry arranged in a multi-cell structure having a plurality of conversion cells, each conversion cell including one or more converter output terminals, the conversion circuitry being configured to convert power received at a first voltage for delivery via the converter output terminals of the plurality of conversion cells at a second lower voltage, the converter output terminals being arranged in a first pattern having a first spacing between the converter output terminals; providing an interconnection module having x-input terminals arranged on a first side of the interconnection module in a pattern configured to align with the first pattern of converter output terminals, and x-output terminals arranged on a surface of a second opposite side of the interconnection module in a second pattern arranged within the die footprint and configured to align with the power input terminals of the semiconductor device, the second pattern having a second spacing between x-output terminals, the second spacing being different than the first spacing, the x-input terminals being electrically connected to the x-output terminals; assembling the power conversion module to the first side of the interconnection module with each converter output terminal mated with and electrically connected to a respective x-input terminal; wherein the interconnection module is configured to provide electrical and mechanical translation between the converter output terminals arranged in the first pattern and the power input terminals of the semiconductor device arranged in the second pattern; wherein the power conversion module and the interconnection module are stacked to form a module sandwich including the power conversion module in a first layer, electrical connections between the converter output terminals and the x-input terminals in a second layer, and the interconnection module in a third layer.

Claim 27

27. A method of making power converters, the method comprising: assembling an encapsulated panel including a printed circuit board (“PCB”) having electronic components mounted to the PCB and a plurality of conductive features enclosed within the panel and unexposed to an exterior surface of the panel, the panel comprising one or more power conversion modules having boundaries defined by one or more predetermined cut lines; configuring each of the one or more power conversion modules in a multi-cell structure having a plurality of conversion cells, each conversion cell including one or more converter output nodes arranged in a first pattern having a first spacing between the output nodes, and wherein each output node is electrically connected to a respective conductive feature; selectively forming a plurality of holes in the exterior surface of the panel, each hole being formed at a respective predetermined location aligned with a respective output node, spaced apart from the cut lines, and exposing within the hole the respective conductive feature; selectively forming one or more conductive metal layers on the exterior surface of the panel including within the plurality of holes, the one or more conductive metal layers within each hole being in electrical contact with the respective conductive feature, to form a plurality of electrical contacts on the exterior surface of the panel; patterning the one or more conductive metal layers on the exterior surface to electrically isolate at least one electrical contact from one or more of the plurality of electrical contacts; cutting the panel along the one or more cut lines to singulate the one or more power conversion modules, each singulated power conversion module having a respective plurality of the electrical contacts formed on the exterior surface of the module.

Claim 34

34. A method of making electronic assemblies, the method comprising: providing an electronic module having electronic circuitry including circuit terminals arranged in a first pattern having a first spacing between the circuit terminals; providing an interconnection module having x-input terminals arranged on a first surface of the interconnection module in a pattern configured to align with the first pattern of circuit terminals, and x-output terminals arranged on a second surface in a second pattern configured to align with external terminals of a third electronic device, the second pattern having a second spacing between the x-output terminals, the second spacing being different than the first spacing, the x-input terminals being electrically connected to the x-output terminals; assembling the electronic module to the first surface of the interconnection module with each circuit terminal mated with and electrically connected to a respective x-input terminal; wherein the interconnection module is configured to provide electrical and mechanical translation between the circuit terminals arranged in the first pattern and the external terminals of the third electronic device arranged in the second pattern; wherein the electronic module and the interconnection module are stacked to form a module sandwich including the electronic module in a first layer, electrical connections between the circuit terminals and the x-input terminals in a second layer, and the interconnection module in a third layer; assembling a first panel comprising a plurality of unsingulated electronic modules; assembling a second panel comprising a plurality of unsingulated interconnection modules; wherein the assembling of the electronic module and the interconnection module is performed using the first and second panels prior to singulation to form a panel sandwich and further comprises dispensing a curable adhesive compound between the first and second panels and forming solder connections between each circuit terminal and each respective x-input terminal; and cutting the panel sandwich along predetermined cut lines to singulate a plurality of the module sandwiches.

Claim 37

37. A method of forming modular circuit assemblies, the method comprising: assembling first and second encapsulated panels each including a first multilayer printed circuit board (“PCB”) having a plurality of conductive layers, a first plurality of electronic components mounted to a first surface of the PCB, and a first layer of cured encapsulant covering the first plurality of electronic components and the surface of the PCB, the first layer of cured encapsulant forming a first exterior surface of the encapsulated panel, the encapsulated panel comprising a plurality of unsingulated electronic modules, each electronic module having perimeter boundaries defined by one or more predetermined cut lines; selectively forming a plurality of terminal holes in the first exterior surface of each panel through the first layer at predetermined locations within the perimeter boundaries of each electronic module, each terminal hole being spaced apart from the cut lines and exposing within the terminal hole a respective conductive feature; selectively forming one or more conductive metal layers on the first exterior surface of each panel including within the plurality of terminal holes, the one or more conductive metal layers within each terminal hole being in electrical contact with the respective conductive feature; patterning the one or more conductive metal layers on the exterior surface, to form a plurality of electrical contacts on the exterior surface of each panel electrically isolated from at least one other electrical contact in the plurality of electrical contacts; assembling the first and second encapsulated panels with electrical contacts on the first panel aligned and mated with respective electrical contacts on the second panel to form a panel stack, the panel stack comprising a plurality of un-singulated module stacks, each module stack including an unsingulated electronic module in the first panel and a respective unsingulated electronic module in the second panel; and cutting the panel stack along the one or more cut lines to singulate the plurality of electronic module stacks.

Claim 40

40. An apparatus comprising: a semiconductor device having power input terminals; a power conversion module having conversion circuitry arranged in a multi-cell structure having a plurality of conversion cells, each conversion cell including one or more converter output terminals, the conversion circuitry being configured to convert power received at a first voltage for delivery via the converter output terminals of the plurality of conversion cells at a second lower voltage, the converter output terminals being arranged in a first pattern having a first spacing between the converter output terminals; and an interconnection module having x-input terminals arranged on a first surface of the interconnection module in a pattern configured to align with the first pattern of converter output terminals, and x-output terminals arranged on a second surface in a second pattern configured to align with the power input terminals of the semiconductor device, the second pattern having a second spacing between x-output terminals, the second spacing being different than the first spacing, the x-input terminals being electrically connected to the x-output terminals; the converter output terminals of the power conversion module being mated with and electrically connected to respective x-input terminals of the interconnection module; wherein the interconnection module is configured to provide electrical and mechanical translation between the converter output terminals arranged in the first pattern and the power input terminals of the semiconductor device arranged in the second pattern; wherein the power conversion module and the interconnection module are stacked with the power conversion module located at a first level, electrical connections between the converter output terminals and the x-input terminals at a second level, and the interconnection module at a third level.

Claim 45

45. A method of powering a semiconductor device having power input terminals, the method comprising: providing a power conversion module having conversion circuitry arranged in a multi-cell structure having a plurality of conversion cells, each conversion cell including one or more converter output terminals, the conversion circuitry being configured to convert power received at a first voltage for delivery via the converter output terminals of the plurality of conversion cells at a second lower voltage, the converter output terminals being arranged in a first pattern having a first spacing between the converter output terminals; providing an interconnection module having x-input terminals arranged on a first surface of the interconnection module in a pattern configured to align with the first pattern of converter output terminals, and x-output terminals arranged on a second surface in a second pattern configured to align with the power input terminals of the semiconductor device, the second pattern having a second spacing between x-output terminals, the second spacing being different than the first spacing, the x-input terminals being electrically connected to the x-output terminals; providing a plurality of conductive pillars for electrically connecting the converter output terminals with respective x-input terminals; assembling the power conversion module to the interconnection module with each converter output terminal aligned with and electrically connected to a respective x-input terminal by a respective one of the conductive pillars; wherein the interconnection module is configured to provide electrical and mechanical translation between the converter output terminals arranged in the first pattern and the power input terminals of the semiconductor device arranged in the second pattern; wherein the power conversion module and the interconnection module are stacked to form a module sandwich including the power conversion module in a first layer, the conductive pillars connecting the converter output terminals and the x-input terminals in a second layer, and the interconnection module in a third layer; and wherein the x-output terminals are arranged with alternating polarities to reduce interconnection inductance.

Claim 49

49. An apparatus comprising: a semiconductor device, including at least one semiconductor die having a plurality of die power input terminals arranged on a surface of the die and having edges of the semiconductor die defining a die footprint, the semiconductor device having power input terminals arranged within the footprint of the die; a power conversion module having switching power conversion circuitry arranged in a multi-cell structure having a plurality of conversion cells, each conversion cell including one or more converter output terminals, the conversion circuitry being configured to convert power received at a first voltage for delivery via the converter output terminals of the plurality of conversion cells at a second lower voltage, the converter output terminals being arranged in a first pattern having a first spacing between the converter output terminals; and an interconnection module having x-input terminals arranged on a first surface of the interconnection module in a pattern configured to align with the first pattern of converter output terminals, and x-output terminals arranged on a second surface in a second pattern with alternating polarities configured to align with the power input terminals of the semiconductor device, the second pattern having a second spacing between x-output terminals, the second spacing being different than the first spacing, the x-input terminals being electrically connected to the x-output terminals; the converter output terminals of the power conversion module being mated with and electrically connected to respective x-input terminals of the interconnection module; wherein the interconnection module is configured to provide electrical and mechanical translation between the converter output terminals arranged in the first pattern and the power input terminals of the semiconductor device arranged in the second pattern; wherein the power conversion module and the interconnection module are stacked with the power conversion module located at a first level, electrical connections between the converter output terminals and the x-input terminals at a second level, and the interconnection module at a third level.

Claim 53

53. An apparatus for delivering power vertically to a semiconductor die, the die having a plurality of semiconductor power input terminals arranged on a surface of the semiconductor die and having edges of the semiconductor die defining a die footprint, the apparatus comprising: switching power conversion circuitry arranged on a first substrate having a plurality of switching power conversion cells and a plurality of converter output terminals, the switching power conversion circuitry being configured to convert power received at a first voltage for delivery via the converter output terminals at a second lower voltage; translation interconnections including X-input terminals configured and arranged to align with and electrically connect to the converter output terminals, a plurality of X-output terminals configured and arranged with alternating polarities to align with respective power input terminals of the semiconductor die, and a plurality of vertical conductors to make electrical connections to the X-output terminals; a capacitive array arranged between the power conversion circuitry and the semiconductor die and electrically connected to the translation interconnections to provide energy storage; wherein the translation interconnections are configured to provide electrical and mechanical translation between the converter output terminals and the power input terminals of the semiconductor die; wherein the switching power conversion circuitry, the translation interconnections, and the capacitive array, are each configured and arranged within a respective footprint configured to occupy substantially all of the die footprint, and are together configured and arranged to form a vertical stack configured to occupy substantially all of the die footprint.

Claim 67

67. A vertical power delivery apparatus for a semiconductor die, the semiconductor die having a plurality of semiconductor power input terminals arranged on a surface of the semiconductor die and having edges of the semiconductor die defining a die footprint; the vertical power delivery apparatus comprising in a vertical stack configured to occupy, in whole or in part, the die footprint, the vertical stack comprising: (a) point-of-load (“POL”) switching power conversion circuitry (i) arranged on a substrate within a conversion footprint, (ii) including a plurality of switching power conversion cells connected in parallel to convert power from an input at an input voltage for delivery to the semiconductor power input terminals at a die voltage, (iii) the input voltage being at least five times higher than the die voltage, and (iv) the conversion footprint being configured to occupy, in whole or in part, the die footprint; (b) interdigitated output terminals (i) electrically connected to receive power from the switching power conversion cells, (ii) configured within a terminal footprint to match the plurality of semiconductor power input terminals, (iii) the terminal footprint being configured to occupy, in whole or in part, the die footprint; and (c) a capacitive array (i) arranged between the power conversion circuitry and the semiconductor die, (ii) within a filter footprint configured to occupy, in whole or in part, the die footprint and (iii) electrically connected to the interdigitated output terminals.

Claim 68

68. A vertical power delivery apparatus for a semiconductor die, the semiconductor die having a plurality of semiconductor power input terminals arranged on a surface of the semiconductor die and having edges of the semiconductor die defining a die footprint; the vertical power delivery apparatus comprising in a vertical stack configured to occupy, in whole or in part, the die footprint, the vertical stack comprising: (a) point-of-load (“POL”) switching power conversion circuitry (i) arranged on a substrate within a conversion footprint, (ii) including a plurality of switching power conversion cells connected in parallel to convert power from an input at an input voltage to the semiconductor power input terminals at a die voltage, (iii) the input voltage being at least five times higher than the die voltage, (iv) the conversion footprint being configured to occupy, in whole or in part, the die footprint; (b) interdigitated output terminals (i) electrically connected to receive power from the switching power conversion cells, (ii) configured within a terminal footprint to match the plurality of semiconductor power input terminals, (iii) the terminal footprint being configured to occupy, in whole or in part, the die footprint; (c) a capacitive array (i) arranged between the power conversion circuitry and the semiconductor die, (ii) within a filter footprint configured to occupy, in whole or in part, the die footprint, and (iii) electrically connected to the interdigitated output terminals; and (d) a plurality of vertical conductors arranged within the die footprint to connect the interdigitated output terminals to the switching power conversion cells.

Art before the examiner

134 references of record, 1 cited by the examiner.

Everything listed here was before the Office and is what a challenge must go beyond. Art the examiner never saw is where an invalidity search starts.

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Classification

  • H02M1/08primary — Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
  • H02M3/33576primary — Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
  • H01L24/26
  • H02M1/0074 — Plural converter units whose inputs are connected in series
  • H02M1/008 — Plural converter units for generating at two or more independent and non-parallel outputs, e.g. systems with plural point of load switching regulators
  • H02M2001/0074
  • H05K1/0298 — Multilayer circuits
  • H05K1/144 — Stacked arrangements of planar printed circuit boards
  • H10W72/248 — Top-view layouts, e.g. mirror arrays
  • H10W72/252 — Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
  • H10W72/29 — Bond pads specially adapted therefor
  • H10W72/30 — Die-attach connectors
  • H10W72/9445 — Top-view layouts, e.g. mirror arrays
  • H10W90/724 — Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Family

  • US10903734B1 — B1 (2021)
  • US11398770B1 — B1 (2022)

Abstract

Encapsulated electronic modules having complex contact structures may be formed by encapsulating panels containing a substrate comprising pluralities of electronic modules delineated by cut lines and having conductive interconnects buried within terminal holes and other holes drilled in the panel within the boundaries of the cut lines. Slots may be cut in the panel along the cut lines. The interior of the holes, as well as surfaces within the slots and on the surfaces of the panel may be metallized, e.g. by a series of processes including plating. Solder may be dispensed into the holes for surface mounting. Two or more panels may be stacked prior to singulation to form module stacks. Multi-cell converters having a large cell pitch may be combined with an interconnection module to provide vertical power delivery to semiconductor devices through a semiconductor power grid having a small pitch. The converters and interconnection modules may be fabricated in panels and stacked prior to singulation.

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