US 6,742,071 Real-time I/O processor used to implement bus interface protocols
27 defendants · 27 suits · updated October 6, 2026
Also cited as U.S. Patent No. 6,742,071 · US6742071B1 · US 6,742,071 B1 · 6742071 · the '071 patent
Near Field Electronics LLC has filed 27 patent-infringement suits on US 6,742,071, "Real-time I/O processor used to implement bus interface protocols" since June 12, 2026, all in the E.D. Tex., against 27 distinct defendants including Shake Shack Inc., The Michaels Companies Inc. and Zagg Inc.. The patent was granted May 25, 2004 on a priority date of July 25, 2000. Its abstract opens: "A circuit that may be configured to store data and interface with an external device." The examiner cited 8 references during prosecution.
- Assignee
- Near Field Electronics LLC
- Priority date
- July 25, 2000
- Granted
- May 25, 2004
- Expires
- July 25, 2020
- Status
- Expired - Lifetime
- Claims
- 17 (4 independent)
- Inventors
- John Boynton, Scott Swindle
- Full text
- Google Patents
The suits
27 cases · E.D. Tex. (27)
| Filed | Defendant | Plaintiff | Court | Docket |
|---|---|---|---|---|
| 2026-06-12 | Shake Shack Inc. | Near Field Electronics LLC | E.D. Tex. | 4:26-cv-00643 |
| 2026-06-12 | The Michaels Companies Inc. | Near Field Electronics LLC | E.D. Tex. | 4:26-cv-00642 |
| 2026-07-20 | Zagg Inc. | Near Field Electronics LLC | E.D. Tex. | 4:26-cv-00884 |
| 2026-07-20 | Zara USA, Inc. | Near Field Electronics LLC | E.D. Tex. | 4:26-cv-00885 |
| 2026-07-20 | Zumiez Inc. | Near Field Electronics LLC | E.D. Tex. | 4:26-cv-00886 |
| 2026-07-23 | Whole Foods Market Services LLC | Near Field Electronics LLC | E.D. Tex. | 4:26-cv-00923 |
| 2026-07-23 | Yum! Brands, Inc. | Near Field Electronics LLC | E.D. Tex. | 4:26-cv-00924 |
| 2026-08-12 | Best Buy Co., Inc. | Near Field Electronics LLC | E.D. Tex. | 4:26-cv-01062 |
| 2026-08-19 | American Eagle Outfitters, Inc. | Near Field Electronics LLC | E.D. Tex. | 4:26-cv-01098 |
| 2026-08-19 | Bridgestone Americas, Inc. | Near Field Electronics LLC | E.D. Tex. | 4:26-cv-01101 |
| 2026-08-19 | Caleres, Inc. dba Allen Edmonds | Near Field Electronics LLC | E.D. Tex. | 4:26-cv-01097 |
| 2026-08-19 | Carter's, Inc. | Near Field Electronics LLC | E.D. Tex. | 4:26-cv-01096 |
| 2026-08-19 | Gucci America, Inc. | Near Field Electronics LLC | E.D. Tex. | 4:26-cv-01102 |
| 2026-08-19 | Kirkland's Stores, Inc. | Near Field Electronics LLC | E.D. Tex. | 4:26-cv-01103 |
| 2026-08-19 | Sally Beauty Supply LLC | Near Field Electronics LLC | E.D. Tex. | 4:26-cv-01104 |
| 2026-08-19 | The Buckle, Inc. | Near Field Electronics LLC | E.D. Tex. | 4:26-cv-01099 |
| 2026-08-19 | The Finish Line, Inc. | Near Field Electronics LLC | E.D. Tex. | 4:26-cv-01100 |
| 2026-08-19 | TravisMathew, LLC | Near Field Electronics LLC | E.D. Tex. | 4:26-cv-01105 |
| 2026-09-08 | Dr. Martens Airwair USA LLC | Near Field Electronics LLC | E.D. Tex. | 4:26-cv-01224 |
| 2026-09-08 | Euromarket Designs, Inc. | Near Field Electronics LLC | E.D. Tex. | 4:26-cv-01223 |
| 2026-09-08 | Fitness International, LLC d/b/a LA Fitness | Near Field Electronics LLC | E.D. Tex. | 4:26-cv-01227 |
| 2026-09-08 | Hat World, Inc. | Near Field Electronics LLC | E.D. Tex. | 4:26-cv-01229 |
| 2026-09-08 | James Avery Craftsman, Inc. | Near Field Electronics LLC | E.D. Tex. | 4:26-cv-01226 |
| 2026-09-08 | Laderach (USA) Inc. | Near Field Electronics LLC | E.D. Tex. | 4:26-cv-01228 |
| 2026-09-08 | Potbelly Sandwich Works, LLC | Near Field Electronics LLC | E.D. Tex. | 4:26-cv-01230 |
| 2026-09-08 | The Children's Place, Inc. | Near Field Electronics LLC | E.D. Tex. | 4:26-cv-01222 |
| 2026-09-08 | The Yankee Candle Company, Inc. | Near Field Electronics LLC | E.D. Tex. | 4:26-cv-01231 |
Docket links open the public record on CourtListener. Filing dates are the complaint's.
Independent claims
What is actually asserted, verbatim.
1. A circuit comprising: a memory configured to generate a plurality of first control signals in response to a state signal; a first circuit configured to generate said state signal conveying one of a plurality of states in response to a second control signal; and an interface circuit configured to (i) interface with an external bus, (ii) drive at least one output control signal of said first control signals onto said external bus, (iii) generate said second control signal in response to both an input signal received from said external bus and at least one internal control signal of said first control signals and (iv) generate a signal in response to at least one of said first control signals.
9. A circuit comprising: a memory configured to generate a plurality of first control signals in response to a state signal; a first circuit configured to generate a second control signal in response to at least one of a read signal and a write signal; and an interface circuit configured to (i) interface to an external bus, (ii) drive at least one output control signal of said first control signals to said external bus, (iii) generate said state signal conveying one of a plurality of states in response to (a) at least one internal control signal of said first control signals, (b) said second control signal and (c) an input signal received from said external bus and (iv) generate a signal in response to at least one of said first control signals.
13. A method for providing an interface to an external bus, comprising the steps of: (A) executing an instruction defining a plurality of first control signals in response to a current state of a plurality of states; (B) driving at least one output control signal of said first control signals onto said external bus while (i) waiting a predetermined number of clock periods defined by a wait type of said instruction and (ii) branching to a next instruction defined by a branch type of said instruction comprising a plurality of branch conditions; (C) generating a second control signal in response both to an input signal received from said external bus and at least one internal control signal of said first control signals; and (D) updating said current state in response to said second control signal.
15. A method for providing an interface to an external bus, comprising the steps of: (A) generating a plurality of first control signals in response to a current state of a processor; (B) progressing to a next state based on said current state, at least one internal control signal of said first control signals and an input signal received from said external bus; (C) driving at least one output control signal of said first controls signals onto said external bus; and (D) updating said current state to said next state.
Art before the examiner
13 references of record, 8 cited by the examiner.
Everything listed here was before the Office and is what a challenge must go beyond. Art the examiner never saw is where an invalidity search starts.
Examiner-cited
- US4835491A — Clock signal generation (Hewlett-Packard Company)
- US5175820A — Apparatus for use with a computing device controlling communications with a plurality of peripheral devices including a feedback bus to indicate operational modes (Advanced Micro Devices, Inc.)
- US5737564A — Cache memory system having multiple caches with each cache mapped to a different area of main memory to avoid memory contention and to lessen the number of cache snoops (Advanced Micro Devices, Inc.)
- US5850553A — Reducing the number of executed branch instructions in a code sequence (Hewlett-Packard Company)
- US6000037A — Method and apparatus for synchronizing data transfer (Lsi Logic Corporation)
- US6073223A — Memory controller and method for intermittently activating and idling a clock signal for a synchronous memory (Hewlett-Packard Company)
- US6192070B1 — Universal modem for digital video, audio and data communications (Mitsubishi Electric Research Laboratories, Inc.)
- US6490638B1 — General purpose bus with programmable timing (Advanced Micro Devices, Inc.)
Applicant-cited and other (5)
- US4689740A — Two-wire bus-system comprising a clock wire and a data wire for interconnecting a number of stations
- WO1996017305A2 — Circuit comprising a data communication bus
- US5559502A — Two-wire bus system comprising a clock wire and a data wire for interconnecting a number of stations and allowing both long-format and short-format slave addresses
- WO1998034376A2 — Communications bus using different transmission rates
- WO1999009712A2 — Electronic apparatus with a bus
Classification
- G06F13/4027primary — Coupling between buses using bus bridges
Family
- US6742071B1 — B1 (2004)
Abstract
A circuit that may be configured to store data and interface with an external device. The circuit may provide one or more control signals to the external device.
Also asserted by Near Field Electronics LLC
- US 6,691,201 — Dual mode USB-PS/2 device (27 defendants)
- US 6,959,350 — Configurable USB interface with virtual register architecture (27 defendants)
- US 6,996,727 — Power supply for universal serial bus interface with programmable bus pullup resistor (27 defendants)
- US 7,373,531 — Signal detection method, frequency detection method, power consumption control method, signal detecting device, frequency detecting device, power consumption control device and electronic apparatus (27 defendants)
Named in one of these suits? A prior-art search is commissioned once and serves every defendant who shares it. The examiner's own search record is free on the tools page, and your first preliminary search is free — one claim, back within 24 hours — so you know whether there is art the Office never saw before anyone pays for more. Flat fees: $2,500$899 for the independent claims, $5,000$1,500 for every asserted claim.
This page is assembled from public records — federal court dockets and the patent's own file — and is updated as the case list changes. It states what the record shows and is not an opinion on the validity or infringement of any claim. Patent data via Google Patents; docket data via CourtListener.