US 7,057,960 Method and architecture for reducing the power consumption for memory devices in refresh operations
9 defendants · 9 suits · updated October 6, 2026
Also cited as U.S. Patent No. 7,057,960 · US7057960B1 · US 7,057,960 B1 · 7057960 · the '960 patent
InnoMemory, LLC has filed 9 patent-infringement suits on US 7,057,960, "Method and architecture for reducing the power consumption for memory devices in refresh operations" since June 17, 2026, all in the E.D. Tex., against 9 distinct defendants including Elite Semiconductor Microelectronics Technology Inc., Innodisk Corporation and Netac Technology Co., Ltd.. The patent was granted June 6, 2006 on a priority date of March 4, 2002. Its abstract opens: "A method for reducing power consumption during background operations in a memory array with a plurality of sections comprising the steps of (i) controlling the background operations in one or more sections of the memory array in response to one or more…" The examiner cited 6 references during prosecution.
- Assignee
- Innomemory LLC
- Priority date
- March 4, 2002
- Granted
- June 6, 2006
- Expires
- March 4, 2022
- Status
- Expired - Lifetime
- Claims
- 27 (6 independent)
- Inventors
- Timothy E. Fiscus, David E. Chapman, Richard M. Parent
- Full text
- Google Patents
The suits
9 cases · E.D. Tex. (9)
| Filed | Defendant | Plaintiff | Court | Docket |
|---|---|---|---|---|
| 2026-06-17 | Elite Semiconductor Microelectronics Technology Inc. | InnoMemory, LLC | E.D. Tex. | 2:26-cv-00481 |
| 2026-06-17 | Innodisk Corporation | InnoMemory, LLC | E.D. Tex. | 2:26-cv-00482 |
| 2026-06-17 | Netac Technology Co., Ltd. | InnoMemory, LLC | E.D. Tex. | 2:26-cv-00483 |
| 2026-06-17 | Silicon Power Computer & Communications Inc. | InnoMemory, LLC | E.D. Tex. | 2:26-cv-00484 |
| 2026-06-17 | VIA Technologies, Inc. | InnoMemory, LLC | E.D. Tex. | 2:26-cv-00485 |
| 2026-08-25 | Acrelec Group SAS | InnoMemory, LLC | E.D. Tex. | 2:26-cv-00743 |
| 2026-08-25 | DFI Inc. | InnoMemory, LLC | E.D. Tex. | 2:26-cv-00745 |
| 2026-08-25 | IEI Integration Corp. | InnoMemory, LLC | E.D. Tex. | 2:26-cv-00746 |
| 2026-08-25 | Kontron Europe GmbH | InnoMemory, LLC | E.D. Tex. | 2:26-cv-00747 |
Docket links open the public record on CourtListener. Filing dates are the complaint's.
Independent claims
What is actually asserted, verbatim.
1. A method for reducing power consumption during background operations in a memory array with a plurality of sections comprising the steps of: controlling said background operations in each of said plurality of sections of said memory array in response to one or more control signals, wherein said one or more control signals are generated in response to a programmable address signal and said background operations can be enabled simultaneously in two or more of said plurality of sections independently of any other section; and presenting said one or more control signals and one or more decoded address signals to one or more periphery array circuits of said plurality of sections.
9. An apparatus comprising: means for controlling a background operation in each of a plurality of sections of a memory array in response to one or more control signals, wherein said one or more control signals are generated in response to a programmable address signal and said background operations can be enabled simultaneously in two or more of said plurality of sections independently of any other section; and means for presenting said one or more control signals and one or more decoded address signals to one or more periphery array circuits of said plurality of sections.
10. An apparatus comprising: a memory array comprising a plurality of sections, wherein each of said sections comprises (i) a plurality of memory cells and (ii) periphery array circuitry configured to control access to said plurality of memory cells; and a control circuit configured to present one or more control signals and one or more decoded address signals to said periphery array circuitry of said plurality of sections, wherein said one or more control signals are generated in response to a programmable address signal, a background operation in each of said plurality of sections is controlled in response to said one or more control signals and said background operation can be enabled simultaneously in two or more of said plurality of sections independently of any other section.
25. A method for reducing power consumption during parity checking in a memory array with a plurality of sections comprising the steps of: controlling said parity checking in one or more of said plurality of sections of said memory array in response to one or more control signals; and presenting said one or more control signals and one or more decoded address signals to one or more periphery array circuits of said one or more sections.
26. A method for reducing power consumption during background operations in a memory array with a plurality of sections comprising the steps of: controlling said background operations in one or more of said plurality of sections of said memory array in response to one or more control signals; presenting said one or more control signals and one or more decoded address signals to one or more periphery array circuits of said one or more sections; and generating a memory cell selection signal comprising a binary numerical representation configured such that a single bit changes between successive numbers in response to a refresh enable signal.
27. An apparatus comprising: a memory array comprising a plurality of sections, wherein each of said sections comprises (i) a plurality of memory cells and (ii) periphery array circuitry configured to control access to said plurality of memory cells; and a control circuit configured to present one or more control signals and one or more decoded address signals to said periphery array circuitry of said plurality of sections, wherein (a) a background operation in each of said plurality of sections (i) is controlled in response to said one or more control signals and (ii) can be enabled independently of any other section and (b) said control circuit comprises (i) an array control circuit configured to generate said one or more control signals in response to one or more block address signals and a refresh enable signal and (ii) a register configured to store said one or more block address signals.
Art before the examiner
28 references of record, 6 cited by the examiner.
Everything listed here was before the Office and is what a challenge must go beyond. Art the examiner never saw is where an invalidity search starts.
Examiner-cited
- US5251178A — Low-power integrated circuit memory (Childers Jimmie D)
- US5535169A — Semiconductor memory device (Fujitsu Limited)
- US5798976A — Semiconductor memory device with reduced current consumption in data holding mode (Mitsubishi Denki Kabushiki Kaisha)
- US6381188B1 — DRAM capable of selectively performing self-refresh operation for memory bank (Samsung Electronics Co., Ltd.)
- US6560153B2 — Semiconductor device, method for refreshing the same, system memory, and electronics apparatus (Seiko Epson Corporation)
- US6590822B2 — System and method for performing partial array self-refresh operation in a semiconductor memory device (Samsung Electronics Co., Ltd.)
Applicant-cited and other (22)
- US4570242A — Dynamic random-access memory
- US5262998A — Dynamic random access memory with operational sleep mode
- US5331601A — DRAM variable row select
- US5345574A — Memory card having controller providing adjustable refresh to a plurality of DRAMs
- US5442588A — Circuits and methods for refreshing a dual bank memory
- US5499213A — Semiconductor memory device having self-refresh function
- US5640357A — Storage device using dynamic RAM
- US5831921A — Semiconductor memory device having signal generating circuitry for sequentially refreshing memory cells in each memory cell block in a self-refresh mode
- US5875143A — Dynamic memory device with refresh circuit and refresh method
- US5894446A — Semiconductor memory device operable with reduced current consumption immediately after power-on
- US5959924A — Method and circuit for controlling an isolation gate in a semiconductor memory device
- US5970507A — Semiconductor memory device having a refresh-cycle program circuit
- US5999471A — Semiconductor memory device having a refresh function and a method for refreshing the same
- US6067261A — Timing of wordline activation for DC burn-in of a DRAM with the self-refresh
- US6118719A — Self-initiated self-refresh mode for memory modules
- US6137742A — Semiconductor memory device having self-refresh control circuit
- US6141278A — Semiconductor memory device allowing fast successive selection of word lines in a test mode operation
- US6215714B1 — Semiconductor memory device capable of reducing power consumption in self-refresh operation
- US6246619B1 — Self-refresh test time reduction scheme
- US6256244B1 — Self refresh apparatus in semiconductor memory device
- US6275895B1 — Memory refreshing system
- US6295243B1 — Semiconductor device
Classification
- G11C11/406primary — Management or control of the refreshing or charge-regeneration cycles
Family
- US7057960B1 — B1 (2006)
- US6618314B1 — B1 (2003)
Abstract
A method for reducing power consumption during background operations in a memory array with a plurality of sections comprising the steps of (i) controlling the background operations in one or more sections of the memory array in response to one or more control signals and (ii) presenting the one or more control signals and one or more decoded address signals to one or more periphery array circuits of the one or more sections.
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