US 7,599,231 Adaptive regulator for idle state in a charge pump circuit of a memory device
3 defendants · 3 suits · updated October 6, 2026
Also cited as U.S. Patent No. 7,599,231 · US7599231B2 · US 7,599,231 B2 · 7599231 · the '231 patent
Crestone IP Management, LLC has filed 3 patent-infringement suits on US 7,599,231, "Adaptive regulator for idle state in a charge pump circuit of a memory device" since July 16, 2026, 2 of them in the E.D. Tex., against 3 distinct defendants including Apple Inc., HP Inc. and Samsung Electronics Co., Ltd.. The patent was granted October 6, 2009 on a priority date of October 11, 2006. Its abstract opens: "An apparatus and method for improving the performance of an electronic device is disclosed." The examiner cited 6 references during prosecution.
- Assignee
- Crestone Ip Management LLC
- Priority date
- October 11, 2006
- Granted
- October 6, 2009
- Expires
- October 11, 2026
- Status
- Active
- Claims
- 19 (3 independent)
- Inventors
- Marco Passerini, Stefano Sivero, Andrea Sacco, Monica Marziani
- Full text
- Google Patents
The suits
3 cases · E.D. Tex. (2) · W.D. Tex. (1)
| Filed | Defendant | Plaintiff | Court | Docket |
|---|---|---|---|---|
| 2026-07-16 | Apple Inc. | Crestone IP Management, LLC | W.D. Tex. | 1:26-cv-01976 |
| 2026-07-16 | HP Inc. | Crestone IP Management, LLC | E.D. Tex. | 2:26-cv-00586 |
| 2026-07-16 | Samsung Electronics Co., Ltd. | Crestone IP Management, LLC | E.D. Tex. | 2:26-cv-00584 |
Docket links open the public record on CourtListener. Filing dates are the complaint's.
Independent claims
What is actually asserted, verbatim.
1. An apparatus comprising: at least one memory element coupled to a modify node, a first node, and a read node, the read node to receive a voltage having a predetermined voltage level and to selectively provide information stored in the at least one memory element, the first node having a first capacitance and a first capacitance voltage level; and an adaptive voltage generator coupled to the modify node to selectively modify information in the at least one memory element coupled to the modify node, wherein the adaptive voltage generator is configured to maintain the first node and the modify node at the predetermined voltage level when switching between a modify operation and a read operation in the at least one memory element.
6. An apparatus comprising: at least one memory element coupled to a modify node, a first node, and a read node, the read node to selectively provide information stored in the at least one memory element, the first node having a first capacitance and a first capacitance voltage level; an adaptive voltage generator coupled to the modify node to selectively modify information in the at least one memory element coupled to the modify node, wherein the adaptive voltage generator is configured to maintain the first node at a predetermined voltage level when switching between a modify operation and a read operation in the at least one memory element; a first switch coupled between the read node and the first node; a second switch coupled between the first node and the modify node; a third switch coupled between the first node and a second node; a fourth switch coupled between the second node and a ground node; and a second capacitance coupled between the second node and the ground node.
12. An apparatus comprising: a read node to receive a first voltage; a modify node; a switching stage coupled between the read node and the modify node, the switching stage including a first node; and an adaptive voltage generator configured to apply a second voltage having a first value corresponding to a value of the first voltage to the modify node before the switching stage couples the first node to the modify node.
Art before the examiner
24 references of record, 6 cited by the examiner.
Everything listed here was before the Office and is what a challenge must go beyond. Art the examiner never saw is where an invalidity search starts.
Examiner-cited
- US4451748A — MOS High voltage switching circuit (Intel Corporation)
- US5969557A — Delay circuit, oscillation circuit and semiconductor memory device (Kabushiki Kaisha Toshiba)
- US6172553B1 — High voltage steering network for EEPROM/FLASH memory (Cypress Semiconductor Corp.)
- US6411554B1 — High voltage switch circuit having transistors and semiconductor memory device provided with the same (Mitsubishi Denki Kabushiki Kaisha)
- US7042788B2 — Power supply circuit and semiconductor storage device with the power supply circuit (Nec Electronics Corporation)
- US20070076492A1 — Storage device and control method thereof (Hideki Arakawa)
Applicant-cited and other (18)
- US5303188A — Semiconductor memory device regulable in access time after fabrication thereof
- US5410680A — Solid state memory device having serial input/output
- JPH09134794A — Signal processor
- US5949666A — Staircase adaptive voltage generator circuit
- US6259632B1 — Capacitive compensation circuit for the regulation of the word line reading voltage in non-volatile memories
- US6278633B1 — High bandwidth flash memory that selects programming parameters according to measurements of previous programming operations
- US6420215B1 — Three-dimensional memory array and method of fabrication
- US6549450B1 — Method and system for improving the performance on SOI memory arrays in an SRAM architecture system
- US6639838B2 — Non-volatile memory architecture and integrated circuit comprising a corresponding memory
- US20040245975A1 — High voltage shunt regulator for flash memory
- US6842381B2 — Method of marginal erasure for the testing of flash memories
- US6906576B2 — High precision digital-to-analog converter with optimized power consumption
- US6944059B2 — High voltage generation and regulation circuit in a memory device
- US7030684B2 — High voltage switch circuit of semiconductor device
- US20060083062A1 — Block switch in flash memory device
- US20060114721A1 — Method and system for regulating a program voltage value during multilevel memory device programming
- US20060133149A1 — Methods and circuits for generating a high voltage and related semiconductor memory devices
- WO2008045411A2 — Adaptive regulator for idle state in a charge pump circuit of a memory device
Classification
- G11C7/02primary — Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
- G11C5/145 — Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
Family
- US7599231B2 — B2 (2009)
- US20080089140A1 — A1 (2008)
- US20100074030A1 — A1 (2010)
- US7983098B2 — B2 (2011)
- 3 foreign family members: TW200828311A, WO2008045411A3, WO2008045411A2
Abstract
An apparatus and method for improving the performance of an electronic device is disclosed. An idle voltage state is introduced by an adaptive voltage generator when providing or removing a high voltage signal from a line or a node in a circuit. The idle state reduces the undesirable effects of switching disturbances caused by sudden voltage changes in a line or node.
Also asserted by Crestone IP Management, LLC
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- US 9,228,534 — Variable contour nacelle assembly for a gas turbine engine (3 defendants)
- US 9,288,534 — Systems and methods for operating media devices (3 defendants)
Named in one of these suits? A prior-art search is commissioned once and serves every defendant who shares it. The examiner's own search record is free on the tools page, and your first preliminary search is free — one claim, back within 24 hours — so you know whether there is art the Office never saw before anyone pays for more. Flat fees: $2,500$899 for the independent claims, $5,000$1,500 for every asserted claim.
This page is assembled from public records — federal court dockets and the patent's own file — and is updated as the case list changes. It states what the record shows and is not an opinion on the validity or infringement of any claim. Patent data via Google Patents; docket data via CourtListener.