Patents in suit

US 9,001,581 Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making

8 defendants · 8 suits · updated October 8, 2026

Also cited as U.S. Patent No. 9,001,581 · US9001581B2 · US 9,001,581 B2 · 9001581 · the '581 patent

ExactoJoin LLC has filed 8 patent-infringement suits on US 9,001,581, "Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making" since September 17, 2026, all in the E.D. Tex., against 8 distinct defendants including Apacer Technology Inc., ASRock Incorporation and ATP Electronics Taiwan Inc.. The patent was granted April 7, 2015 on a priority date of November 29, 2007. Its abstract opens: "An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data." The examiner cited 6 references during prosecution.

Assignee
Exactojoin LLC
Priority date
November 29, 2007
Granted
April 7, 2015
Expires
November 29, 2027
Status
Active
Claims
20 (3 independent)
Inventors
Yuniarto Widjaja
Full text
Google Patents

The suits

8 cases · E.D. Tex. (8)

Filed Defendant Plaintiff Court Docket
2026-09-17 Apacer Technology Inc. ExactoJoin LLC E.D. Tex. 2:26-cv-00829
2026-09-17 ASRock Incorporation ExactoJoin LLC E.D. Tex. 2:26-cv-00830
2026-09-17 ATP Electronics Taiwan Inc. ExactoJoin LLC E.D. Tex. 2:26-cv-00831
2026-09-17 BIOSTAR Microtech International Corp. ExactoJoin LLC E.D. Tex. 2:26-cv-00832
2026-09-17 Cactus Technologies Limited ExactoJoin LLC E.D. Tex. 2:26-cv-00833
2026-09-17 Hong Kong Lelegao Technology Co. Limited ExactoJoin LLC E.D. Tex. 2:26-cv-00835
2026-09-17 TSC Auto ID Technology Co., Ltd. ExactoJoin LLC E.D. Tex. 2:26-cv-00837
2026-09-17 Twinhead International Corporation ExactoJoin LLC E.D. Tex. 2:26-cv-00838

Docket links open the public record on CourtListener. Filing dates are the complaint's.

Independent claims

What is actually asserted, verbatim.

Claim 1

1. A semiconductor memory device comprising: a plurality of semiconductor memory cells; at least one contact configured to electrically connect said memory cells to at least one control line, wherein the number of said contacts is less than the number of said memory cells; and said memory device being configured to perform at least one of: injecting charge into or extracting charge out of a portion of at least one of said memory cells to maintain a state of said at least one memory cell.

Claim 10

10. A semiconductor memory device comprising: a plurality of semiconductor memory cells; a first contact configured to electrically connect said memory cells to a first control line; a second contact configured to electrically connect said semiconductor memory cells to a second control line; the plurality of semiconductor memory cells being directly connected to one another so that at least one of said semiconductor memory cells is not directly connected to said contacts; and at least one of said semiconductor memory cells each comprising: a floating body region configured to store data as charge therein to define a state of said semiconductor memory cell.

Claim 16

16. A semiconductor memory device comprising at least two semiconductor memory cells, wherein at least one of said semiconductor memory cells is a contactless semiconductor memory cell, wherein said contactless semiconductor memory cell comprises a floating body region configured to store data as charge therein to define a state of said contactless semiconductor memory cell.

Art before the examiner

104 references of record, 6 cited by the examiner.

Everything listed here was before the Office and is what a challenge must go beyond. Art the examiner never saw is where an invalidity search starts.

Examiner-cited

  • US5113238A — Contactless non-volatile memory array cells (Wang Chen Chin)
  • US5357465A — Single transistor EEPROM memory cell (Nexcom Technology, Inc.)
  • US5796142A — SOI compact contactless flash memory cell (United Microelectronics Corporation)
  • US5946240A — Nonvolatile semiconductor memory device and method of manufacturing the same (Nec Corporation)
  • US5986934A — Semiconductor memory array with buried drain lines and methods therefor (Winbond Electronics Corp.I)
  • US6211547B1 — Semiconductor memory array with buried drain lines and processing methods therefor (Winbond Electronics Corporation)
Applicant-cited and other (98)
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  • US5748538A — OR-plane memory cell array for flash memory with bit-based write capability, and methods for programming and erasing the memory cell array
  • US5767549A — SOI CMOS structure
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  • US20070284648A1 — Non-volatile memory device and method of manufacturing the same
  • US20080048239A1 — Semiconductor memory device having DRAM cell mode and non-volatile memory cell mode and operation method thereof
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  • US20080123418A1 — Semiconductor memory having both volatile and non-volatile functionality and method of operating
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  • US20090085089A1 — Two-bit flash memory
  • US20090109750A1 — Semiconductor memory having both volatile and non-volatile functionality and method of operating
  • US20090108351A1 — Finfet memory device with dual separate gates and method of operation
  • US7542345B2 — Multi-bit memory cell having electrically floating body transistor, and method of programming and reading same
  • US20090173985A1 — Dense arrays and charge storage devices
  • US20090190402A1 — Integrated SRAM and FLOTOX EEPROM memory device
  • US20090251966A1 — Semiconductor memory having volatile and multi-bit, non-volatile functionality and methods of operating
  • US7609551B2 — Semiconductor memory device
  • US20090316492A1 — Memory cells, memory cell arrays, methods of using and methods of making
  • US20100008139A1 — Memory devices having volatile and non-volatile memory characteristics and methods of operating the same
  • US20100034041A1 — Method of operating semiconductor memory device with floating body transistor using silicon controlled rectifier principle
  • US20100046287A1 — Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating
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Classification

  • G11C11/34primary — Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/404 — Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
  • G11C11/409 — Read-write [R-W] circuits
  • G11C14/0018 — Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a DRAM cell whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
  • G11C16/0416 — Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
  • G11C2211/4016 — Memory devices with silicon-on-insulator cells
  • H01L27/108
  • H01L27/10802
  • H01L27/10826
  • H01L27/115
  • H01L27/11521
  • H01L27/1203
  • H01L27/1211
  • H01L29/7841
  • H01L29/7881
  • H10B12/00 — Dynamic random access memory [DRAM] devices
  • H10B12/20 — DRAM devices comprising floating-body transistors, e.g. floating-body cells
  • H10B12/36 — DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being a FinFET
  • H10B41/30 — Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
  • H10B69/00 — Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
  • H10D30/681 — Floating-gate IGFETs having only two programming levels
  • H10D30/711 — Insulated-gate field-effect transistors [IGFET] having floating bodies
  • H10D62/83 — Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
  • H10D86/201 — Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
  • H10D86/215 — Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI comprising FinFETs

Family

  • US9001581B2 — B2 (2015)
  • US20110032756A1 — A1 (2011)
  • US20150187776A1 — A1 (2015)
  • US20130301349A1 — A1 (2013)
  • US20140159156A1 — A1 (2014)
  • US8711622B2 — B2 (2014)
  • US9209188B2 — B2 (2015)
  • US8514622B2 — B2 (2013)

Abstract

An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.

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This page is assembled from public records — federal court dockets and the patent's own file — and is updated as the case list changes. It states what the record shows and is not an opinion on the validity or infringement of any claim. Patent data via Google Patents; docket data via CourtListener.