Patents in suit

US 8,712,039 Efficient implementation of hash algorithm on a processor

3 defendants · 3 suits · updated October 6, 2026

Also cited as U.S. Patent No. 8,712,039 · US8712039B2 · US 8,712,039 B2 · 8712039 · the '039 patent

Malikie Innovations Ltd. has filed 3 patent-infringement suits on US 8,712,039, "Efficient implementation of hash algorithm on a processor" since August 28, 2026, 2 of them in the W.D. Tex., against 3 distinct defendants including Foundry Digital LLC, Antpool Technologies Limited and ViaBTC Technology Limited. The patent was granted April 29, 2014 on a priority date of April 6, 2011. Its abstract opens: "An efficient implementation of SHA-512, and similarly SHA-384, on an ARM processor." The examiner cited 11 references during prosecution.

Assignee
Malikie Innovations Ltd
Priority date
April 6, 2011
Granted
April 29, 2014
Expires
April 6, 2031
Status
Active
Claims
21 (3 independent)
Inventors
Nevine Maurice Nassif Ebeid, Robert John Lambert
Full text
Google Patents

The suits

3 cases · W.D. Tex. (2) · W.D.N.Y. (1)

Filed Defendant Plaintiff Court Docket
2026-08-28 Foundry Digital LLC Malikie Innovations Ltd. W.D.N.Y. 6:26-cv-06874
2026-09-09 Antpool Technologies Limited Malikie Innovations Ltd. W.D. Tex. 7:26-cv-00371
2026-09-09 ViaBTC Technology Limited Malikie Innovations Ltd. W.D. Tex. 7:26-cv-00372

Docket links open the public record on CourtListener. Filing dates are the complaint's.

Independent claims

What is actually asserted, verbatim.

Claim 1

1. A method for maximizing a number of registers at an end of an iteration of a hash algorithm for use in a next iteration, the method comprising: categorizing and unrolling iterations of an original secure hash algorithm into even iterations and odd iterations; reversing a sequence of computations in the even iterations to those in the odd iterations, said reversing resulting in an average number of words that need to be loaded into the registers per iteration being reduced by at least one-half compared to the original secure hash algorithm; and combining an even iteration and an odd iteration to provide a new iteration of a loop.

Claim 11

11. A system for maximizing a number of registers at an end of an iteration of a hash algorithm for use in a next iteration, the system comprising: a processing circuit configured to categorize and unroll iterations of an original secure hash algorithm into even iterations and odd iterations; reverse a sequence of computations in the even iterations to those in the odd iterations, said reversing resulting in an average number of words that need to be loaded into the registers per iteration being reduced by at least one-half compared to the original secure hash algorithm; and combine an even iteration and an odd iteration to provide a new iteration of a loop.

Claim 21

21. A method for maximizing a number of registers at an end of an iteration of a hash algorithm for use in a next iteration, the method comprising: categorizing and unrolling secure hash algorithm iterations into even iterations and odd iterations; reversing, by a processing circuit, a sequence of computations in the even iterations to those in the odd iterations; combining an even iteration and an odd iteration to provide a new iteration of a loop; and in a last 64 iterations of the secure hash algorithm, keeping an offset constant between a location of a current 8 state words and a pointer to a current w word.

Art before the examiner

13 references of record, 11 cited by the examiner.

Everything listed here was before the Office and is what a challenge must go beyond. Art the examiner never saw is where an invalidity search starts.

Examiner-cited

  • US5297038A — Electronic dictionary and method of codifying words therefor (Sharp Kabushiki Kaisha)
  • US20050050396A1 — Tamper-proofing watermarked computer programs (Auckland Uniservices Limited)
  • US20050114653A1 — Certificate revocation notification systems (Sudia Frank W.)
  • US20070174596A1 — Data processor (Renesas Technology Corp.)
  • US7299355B2 — Fast SHA1 implementation (Broadcom Corporation)
  • US20100049986A1 — Hash value generator (Hitachi, Ltd.)
  • US20100046755A1 — Cryptography related to keys with signature (Fiske Software Llc)
  • US20100250966A1 — Processor and method for implementing instruction support for hash algorithms (Olson Christopher H)
  • US20110231636A1 — Apparatus and method for implementing instruction support for performing a cyclic redundancy check (crc) (Olson Christopher H)
  • US20120144203A1 — Authenticating a User with Hash-Based PIN Generation (At&T Intellectual Property I, L.P.)
  • US20130108038A1 — System and method for a collatz based hash function (Apple Inc.)
Applicant-cited and other (2)
  • US20040260740A1 — System and method of efficiently implementing secure hash algorithm (SHA-1) in digital hardware that accomplishes optimal computation speed using minimal hardware resources
  • US20100086127A1 — Efficient implementation of arithmetical secure hash techniques

Classification

  • H04L9/0643primary — Hash functions, e.g. MD5, SHA, HMAC or f9 MAC
  • G06F9/30007 — Arrangements for executing specific machine instructions to perform operations on data operands
  • H04L9/50 — Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using hash chains, e.g. blockchains or hash trees

Family

  • US8712039B2 — B2 (2014)
  • US20120257742A1 — A1 (2012)
  • 8 foreign family members: EP2601613A1, CA2830779A1, EP2601613A4, CN103477341B, CA2830779C, WO2012135958A1, EP2601613B1, CN103477341A

Abstract

An efficient implementation of SHA-512, and similarly SHA-384, on an ARM processor. The implementation maximizes reuse of the register values between iterations so as to minimize the need to load these values from memory. This is achieved by categorizing the iterations into even and odd ones such that the sequence of computation in the even iteration is reversed in the odd iteration and the register values at the end of one iteration are consumed at the beginning of the following one.

Also asserted by Malikie Innovations Ltd.

  • US 8,532,286 — System and method for reducing the computation and storage requirements for a montgomery-style reduction (4 defendants)
  • US 7,453,856 — Method, apparatus, and communications interface for sending and receiving data blocks associated with different multiple access techniques (3 defendants)
  • US 7,747,934 — Method for selecting low density parity check (LDPC) code used for encoding of variable length data (3 defendants)
  • US 7,917,829 — Low density parity check (LDPC) code (3 defendants)
  • US 8,291,289 — Low density parity check (LDPC) code (3 defendants)
  • US 8,788,827 — Accelerated verification of digital signatures and public keys (3 defendants)
  • US 8,806,197 — Accelerated verification of digital signatures and public keys (3 defendants)

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This page is assembled from public records — federal court dockets and the patent's own file — and is updated as the case list changes. It states what the record shows and is not an opinion on the validity or infringement of any claim. Patent data via Google Patents; docket data via CourtListener.