US 12,250,830 3D semiconductor memory devices and structures

3 defendants · 3 suits · updated October 6, 2026

Also cited as U.S. Patent No. 12,250,830 · US12250830B2 · US 12,250,830 B2 · 12250830 · the '830 patent

MonolithIC 3D Inc. has filed 3 patent-infringement suits on US 12,250,830, "3D semiconductor memory devices and structures" since May 11, 2026, 1 of them in the W.D. Tex., against 3 distinct defendants including NVIDIA Corporation, SK hynix Inc. and MonolithIC 3D Inc.. The patent was granted March 11, 2025 on a priority date of September 21, 2015. Its abstract opens: "A 3D semiconductor device, the device including: a first level including a first single crystal layer and a memory control circuit, the memory control circuit including a plurality of first transistors; a first metal layer overlaying the first single crystal…" The examiner cited 1 reference during prosecution.

Assignee: Monolithic 3D Inc
Priority date: September 21, 2015
Granted: March 11, 2025
Expires: September 21, 2035
Status: Active
Claims: 18 (6 independent)
Inventors: Zvi Or-Bach, Jin-Woo Han
Full text: Google Patents

The suits

3 cases · W.D. Tex. (1) · E.D. Tex. (1) · N.D. Cal. (1)

Filed	Defendant	Plaintiff	Court	Docket
2026-05-11	NVIDIA Corporation	MonolithIC 3D Inc.	W.D. Tex.	7:26-cv-00190
2026-05-11	SK hynix Inc.	MonolithIC 3D Inc.	E.D. Tex.	2:26-cv-00393
2026-06-11	MonolithIC 3D Inc.DJ	Sandisk Corporation	N.D. Cal.	5:26-cv-05641

Docket links open the public record on CourtListener. Filing dates are the complaint's.

Independent claims

What is actually asserted, verbatim.

Claim 1

1. A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer and a memory control circuit, said memory control circuit comprising a plurality of first transistors; a first metal layer overlaying said first single crystal layer; a second metal layer overlaying said first metal layer; a plurality of second transistors disposed atop said second metal layer; a third metal layer disposed atop said plurality of second transistors; and a memory array comprising word-lines and memory cells, wherein said memory array comprises at least four memory mini arrays, wherein at least one of said plurality of second transistors comprises a metal gate, wherein each of said memory cells comprises at least one of said plurality of second transistors, wherein said memory control circuit comprises at least one Look Up Table circuit (“LUT”), and wherein said device comprises a hybrid bonding layer.

Claim 4

4. A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer and a memory control circuit, said memory control circuit comprising a plurality of first transistors; a first metal layer overlaying said first single crystal layer; a second metal layer overlaying said first metal layer; a plurality of second transistors disposed atop said second metal layer; a third metal layer disposed atop said plurality of second transistors; a memory array comprising word-lines and memory cells, wherein said memory array comprises at least four memory mini arrays, wherein at least one of said plurality of second transistors comprises a metal gate, wherein each of said memory cells comprises at least one of said plurality of second transistors, and wherein said memory control circuit comprises at least one Look Up Table circuit (“LUT”); and an upper level disposed atop said third metal layer, wherein said upper level comprises a mono-crystalline silicon layer.

Claim 7

7. A 3D semiconductor device, the device comprising: a first level comprising a single crystal layer and a memory control circuit, said memory control circuit comprising a plurality of first transistors; a first metal layer overlaying said first single crystal layer; a second metal layer overlaying said first metal layer; a plurality of second transistors disposed atop said second metal layer; a third metal layer disposed atop said plurality of second transistors; a memory array comprising word-lines and memory cells, wherein said memory array comprises at least four memory mini arrays, wherein at least one of said plurality of second transistors comprises a metal gate, wherein each of said memory cells comprises at least one of said plurality of second transistors, and wherein said memory control circuit comprises at least one in-out interface control circuit; and a plurality of third transistors disposed atop said plurality of second transistors, wherein at least one of said plurality of second transistors is self-aligned to at least one of said plurality of third transistors, being processed following a same lithography step, and wherein said device comprises a hybrid bonding layer.

Claim 10

10. A 3D semiconductor device, the device comprising: a first level comprising a single crystal layer and a memory control circuit, said memory control circuit comprising a plurality of first transistors; a first metal layer overlaying said first single crystal layer; a second metal layer overlaying said first metal layer; a plurality of second transistors disposed atop said second metal layer; a third metal layer disposed atop said plurality of second transistors; a memory array comprising word-lines and memory cells, wherein said memory array comprises at least four memory mini arrays, wherein at least one of said plurality of second transistors comprises a metal gate, wherein each of said memory cells comprises at least one of said plurality of second transistors, and wherein said memory control circuit comprises at least one in-out interface control circuit; and an upper level disposed atop said third metal layer, wherein said upper level comprises a mono-crystalline silicon layer, and wherein said device comprises a hybrid bonding layer.

Claim 13

13. A 3D semiconductor device, the device comprising: a first level comprising a single crystal layer and a memory control circuit, said memory control circuit comprising a plurality of first transistors; a first metal layer overlaying said first single crystal layer; a second metal layer overlaying said first metal layer; a plurality of second transistors disposed atop said second metal layer; a third metal layer disposed atop said plurality of second transistors; and a memory array comprising word-lines and memory cells, wherein said memory array comprises at least four memory mini arrays, wherein at least one of said plurality of second transistors comprises a metal gate, wherein each of said memory cells comprises at least one of said plurality of second transistors, wherein said memory control circuit comprises at least one in-out interface control circuit, and wherein said device comprises a hybrid bonding layer.

Claim 16

16. A 3D semiconductor device, the device comprising: a first level comprising a single crystal layer and a memory control circuit, said memory control circuit comprising a plurality of first transistors; a first metal layer overlaying said first single crystal layer; a second metal layer overlaying said first metal layer; a plurality of second transistors disposed atop said second metal layer; a plurality of third transistors disposed atop said plurality of second transistors; a third metal layer disposed atop said plurality of third transistors; and a memory array comprising word-lines, wherein said memory array comprises at least four memory mini arrays, wherein each of said at least four memory mini arrays comprises at least four rows by at least four columns of memory cells, wherein at least one of said plurality of second transistors comprises a metal gate, wherein each of said memory cells comprises at least one of said plurality of second transistors, wherein said memory control circuit comprises a memory refresh circuit, and wherein said device comprises a hybrid bonding layer.

Art before the examiner

798 references of record, 1 cited by the examiner.

Everything listed here was before the Office and is what a challenge must go beyond. Art the examiner never saw is where an invalidity search starts.

Examiner-cited

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Classification

G11C16/0416primary — Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
G11C16/10 — Programming or data input circuits
G11C16/16 — Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
G11C16/26 — Sensing or reading circuits; Data output circuits
H01L2224/08145
H01L2224/80006
H01L2224/80895
H01L2224/80896
H01L24/08
H01L24/80
H01L25/0657
H01L25/18
H01L25/50
H01L2924/1431
H01L2924/14511
H10B41/20 — Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
H10B43/20 — EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
H10B80/00 — Assemblies of multiple devices comprising at least one memory device covered by this subclass
H10W80/00 — Direct bonding of chips, wafers or substrates
H10W80/211 — Direct bonding of chips, wafers or substrates using auxiliary members, e.g. aids for protecting the bonding area
H10W80/312 — Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of electrically conductive pads
H10W80/327 — Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers
H10W90/00 — Package configurations
H10W90/792 — Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between multiple chips

Family

US12250830B2 — B2 (2025)
US20240215274A1 — A1 (2024)

Abstract

A 3D semiconductor device, the device including: a first level including a first single crystal layer and a memory control circuit, the memory control circuit including a plurality of first transistors; a first metal layer overlaying the first single crystal layer; a second metal layer overlaying the first metal layer; a plurality of second transistors disposed atop the second metal layer; a third metal layer disposed atop the plurality of second transistors; and a memory array including word-lines and memory cells, where the memory array includes at least four memory mini arrays, where at least one of the plurality of second transistors includes a metal gate, where each of the memory cells includes at least one of the plurality of second transistors, where the memory control circuit includes at least one Look Up Table circuit (“LUT”), and where the device includes a hybrid bonding layer.

Also asserted by MonolithIC 3D Inc.

US 12,362,330 — 3D semiconductor device and structure with connection paths (3 defendants)
US 12,400,961 — 3D semiconductor device and structure with metal layers (3 defendants)
US 12,564,006 — 3D semiconductor device and structure with memory cells and multiple metal layers (3 defendants)

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