US 12,362,330 3D semiconductor device and structure with connection paths
3 defendants · 3 suits · updated October 6, 2026
Also cited as U.S. Patent No. 12,362,330 · US12362330B2 · US 12,362,330 B2 · 12362330 · the '330 patent
MonolithIC 3D Inc. has filed 3 patent-infringement suits on US 12,362,330, "3D semiconductor device and structure with connection paths" since May 11, 2026, 1 of them in the W.D. Tex., against 3 distinct defendants including NVIDIA Corporation, SK hynix Inc. and MonolithIC 3D Inc.. The patent was granted July 15, 2025 on a priority date of January 28, 2014. Its abstract opens: "A 3D semiconductor device, the device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a…" The examiner cited 2 references during prosecution.
- Assignee
- Monolithic 3D Inc
- Priority date
- January 28, 2014
- Granted
- July 15, 2025
- Expires
- January 28, 2034
- Status
- Active
- Claims
- 20 (3 independent)
- Inventors
- Zvi Or-Bach, Brian Cronquist
- Full text
- Google Patents
The suits
3 cases · W.D. Tex. (1) · E.D. Tex. (1) · N.D. Cal. (1)
| Filed | Defendant | Plaintiff | Court | Docket |
|---|---|---|---|---|
| 2026-05-11 | NVIDIA Corporation | MonolithIC 3D Inc. | W.D. Tex. | 7:26-cv-00190 |
| 2026-05-11 | SK hynix Inc. | MonolithIC 3D Inc. | E.D. Tex. | 2:26-cv-00393 |
| 2026-06-11 | MonolithIC 3D Inc.DJ | Sandisk Corporation | N.D. Cal. | 5:26-cv-05641 |
Docket links open the public record on CourtListener. Filing dates are the complaint's.
Independent claims
What is actually asserted, verbatim.
1. A 3D semiconductor device, the device comprising: a first level, wherein said first level comprises a first layer, said first layer comprising first transistors, and wherein said first level comprises a second layer, said second layer comprising first interconnections; a second level overlaying said first level, wherein said second level comprises a plurality of second transistors, wherein said second level comprises a third layer, said third layer comprising first conductive lines; a third level overlaying said second level, wherein said third level comprises a plurality of third transistors, wherein said third level comprises a fourth layer, said fourth layer comprising second conductive lines; and a plurality of connection paths, wherein said plurality of connection paths provides electrical connections at least from a plurality of said first transistors to said plurality of third transistors, and wherein said first level comprises at least one voltage regulator.
8. A 3D semiconductor device, the device comprising: a first level, wherein said first level comprises a first layer, said first layer comprising first transistors, and wherein said first level comprises a second layer, said second layer comprising first interconnections; a second level overlaying said first level, wherein said second level comprises a plurality of second transistors, wherein said second level comprises a third layer, said third layer comprising first conductive lines; a third level overlaying said second level, wherein said third level comprises a plurality of third transistors, wherein said third level comprises a fourth layer, said fourth layer comprising second conductive lines; and a plurality of connection paths, wherein said plurality of connection paths provides electrical connections from a plurality of said first transistors to said plurality of third transistors, and wherein said first level comprises at least one PLL circuit.
15. A 3D semiconductor device, the device comprising: a first level, wherein said first level comprises a first layer, said first layer comprising first transistors, and wherein said first level comprises a second layer, said second layer comprising first interconnections; a second level overlaying said first level, wherein said second level comprises a plurality of second transistors, wherein said second level comprises a third layer, said third layer comprising first conductive lines; a third level overlaying said second level, wherein said third level comprises a plurality of third transistors, wherein said third level comprises a fourth layer, said fourth layer comprising second conductive lines; and a plurality of connection paths, wherein said plurality of connection paths provides electrical connections from a plurality of said first transistors to said plurality of third transistors, and wherein said first level comprises at least one SerDes circuit.
Art before the examiner
2 references of record, 2 cited by the examiner.
Everything listed here was before the Office and is what a challenge must go beyond. Art the examiner never saw is where an invalidity search starts.
Examiner-cited
- US8154910B2 — Full CMOS SRAM (Samsung Electronics Co., Ltd.)
- US11502091B1 — Thin film transistor deck selection in a memory device (Micron Technology, Inc.)
Classification
- H01L25/0657primary
- H10D88/01primary — Manufacture or treatment
- H01L2224/08501
- H01L23/481
- H01L23/50
- H01L24/08
- H01L25/50
- H10D84/0149 — Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
- H10D84/0167 — Manufacturing their channels
- H10D84/038 — Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
- H10D84/83 — Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85 — Complementary IGFETs, e.g. CMOS
- H10D86/01 — Manufacture or treatment
- H10D86/011 — Manufacture or treatment comprising FinFETs
- H10D86/201 — Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
- H10D86/215 — Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI comprising FinFETs
- H10D88/00 — Three-dimensional [3D] integrated devices
- H10D88/101 — Three-dimensional [3D] integrated devices comprising components on opposite major surfaces of semiconductor substrates
- H10W20/20 — Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W40/10 — Arrangements for heating
- H10W42/00 — Arrangements for protection of devices
- H10W72/00 — Interconnections or connectors in packages
- H10W72/01 — Manufacture or treatment
- H10W80/00 — Direct bonding of chips, wafers or substrates
- H10W80/754 — Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding having material changed during the connecting
- H10W90/00 — Package configurations
- H10W90/297 — Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
Family
- US12362330B2 — B2 (2025)
- US20240379624A1 — A1 (2024)
Abstract
A 3D semiconductor device, the device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a plurality of second transistors, where the second level includes a third layer, the third layer including first conductive lines; a third level overlaying the second level, where the third level includes a plurality of third transistors, where the third level includes a fourth layer, the fourth layer including second conductive lines; and a plurality of connection paths, where the plurality of connection paths provides electrical connections at least from a plurality of the first transistors to the plurality of third transistors, and where the first level includes at least one voltage regulator.
Also asserted by MonolithIC 3D Inc.
- US 12,250,830 — 3D semiconductor memory devices and structures (3 defendants)
- US 12,400,961 — 3D semiconductor device and structure with metal layers (3 defendants)
- US 12,564,006 — 3D semiconductor device and structure with memory cells and multiple metal layers (3 defendants)
Named in one of these suits? A prior-art search is commissioned once and serves every defendant who shares it. The examiner's own search record is free on the tools page, and your first preliminary search is free — one claim, back within 24 hours — so you know whether there is art the Office never saw before anyone pays for more. Flat fees: $2,500$899 for the independent claims, $5,000$1,500 for every asserted claim.
This page is assembled from public records — federal court dockets and the patent's own file — and is updated as the case list changes. It states what the record shows and is not an opinion on the validity or infringement of any claim. Patent data via Google Patents; docket data via CourtListener.