Patents in suit

US 12,564,006 3D semiconductor device and structure with memory cells and multiple metal layers

3 defendants · 3 suits · updated October 6, 2026

Also cited as U.S. Patent No. 12,564,006 · US12564006B2 · US 12,564,006 B2 · 12564006 · the '006 patent

MonolithIC 3D Inc. has filed 3 patent-infringement suits on US 12,564,006, "3D semiconductor device and structure with memory cells and multiple metal layers" since May 11, 2026, 1 of them in the W.D. Tex., against 3 distinct defendants including NVIDIA Corporation, SK hynix Inc. and MonolithIC 3D Inc.. The patent was granted February 24, 2026 on a priority date of November 18, 2010. Its abstract opens: "A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, which each include a single crystal channel; a first metal layer with an overlaying second metal layer; a second level including second…" The examiner cited 11 references during prosecution.

Assignee
Monolithic 3D Inc
Priority date
November 18, 2010
Granted
February 24, 2026
Expires
November 18, 2030
Status
Active
Claims
20 (3 independent)
Inventors
Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
Full text
Google Patents

The suits

3 cases · W.D. Tex. (1) · E.D. Tex. (1) · N.D. Cal. (1)

Filed Defendant Plaintiff Court Docket
2026-05-11 NVIDIA Corporation MonolithIC 3D Inc. W.D. Tex. 7:26-cv-00190
2026-05-11 SK hynix Inc. MonolithIC 3D Inc. E.D. Tex. 2:26-cv-00393
2026-06-11 MonolithIC 3D Inc.DJ Sandisk Corporation N.D. Cal. 5:26-cv-05641

Docket links open the public record on CourtListener. Filing dates are the complaint's.

Independent claims

What is actually asserted, verbatim.

Claim 1

1 . A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; a first metal layer, said first metal layer is disposed above or below said first level; a second metal layer overlaying said first metal layer; a second level comprising a plurality of second transistors, said second level overlaying said first level; a third level comprising a plurality of third transistors, said third level overlaying said second level; a fourth level comprising a plurality of fourth transistors, said fourth level overlaying said third level, wherein said second level comprises a plurality of first memory cells, wherein each of said plurality of first memory cells comprises at least one of said second transistors, wherein said fourth level comprises a plurality of second memory cells, wherein each of said plurality of second memory cells comprises at least one of said fourth transistors, wherein said first level comprises memory control circuits, wherein second memory cells comprise at least four memory arrays, wherein each of said four memory arrays are independently controlled, wherein said first level, said second level, said third level, and said fourth level each comprise a dielectric electrical isolation layer disposed in-between and comprise vias and/or thru-layer vias for vertical connection, and wherein at least one of said second transistors comprises a metal gate.

Claim 8

8 . A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; a first metal layer, said first metal layer is disposed above or below said first level; a second metal layer overlaying said first metal layer; a second level comprising a plurality of second transistors, said second level overlaying said first level; a third level comprising a plurality of third transistors, said third level overlaying said second level; a fourth level comprising a plurality of fourth transistors, said fourth level overlaying said third level, wherein said second level comprises a plurality of first memory cells, wherein each of said plurality of first memory cells comprises at least one of said second transistors, wherein said fourth level comprises a plurality of second memory cells, wherein each of said plurality of second memory cells comprises at least one of said fourth transistors, wherein said first level, said second level, said third level, and said fourth level each comprise a dielectric electrical isolation layer disposed in-between and comprise vias and/or thru-layer vias for vertical connection, wherein said first level comprises memory control circuits, and wherein at least one of said second transistors comprises a hafnium oxide gate oxide.

Claim 15

15 . A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; a first metal layer, said first metal layer is disposed above or below said first level; a second metal layer overlaying said first metal layer; a second level comprising a plurality of second transistors, said second level overlaying said first level; a third level comprising a plurality of third transistors, said third level overlaying said second level; a fourth level comprising a plurality of fourth transistors, said fourth level overlaying said third level, wherein said second level comprises a plurality of first memory cells, wherein each of said plurality of first memory cells comprises at least one of said second transistors, wherein said fourth level comprises a plurality of second memory cells, wherein each of said plurality of second memory cells comprises at least one of said fourth transistors, wherein said first level comprises memory control circuits, wherein said first level, said second level, said third level, and said fourth level each comprise a dielectric electrical isolation layer disposed in-between and comprise vias and/or thru-layer vias for vertical connection, wherein at least one of said second transistors is an n type transistor, and wherein at least one of said second transistors is a p type transistor.

Art before the examiner

11 references of record, 11 cited by the examiner.

Everything listed here was before the Office and is what a challenge must go beyond. Art the examiner never saw is where an invalidity search starts.

Examiner-cited

  • US20010015450A1 — Semiconductor integrated circuit and semiconductor integrated circuit device (Tadahiko Sugibayashi)
  • US20050110159A1 — Stacked integrated circuit device including multiple substrates and method of manufacturing the same (Chang-Woo Oh)
  • US20060146233A1 — Image sensor with enlarged photo detection area and method for fabricating the same (Magnachip Semiconductor Ltd.)
  • US20080073635A1 — Semiconductor Memory and Method of Manufacturing the Same (Masahiro Kiyotoshi)
  • US20080160726A1 — Methods of fabricating semiconductor devices including channel layers having improved defect density and surface roughness characteristics (Samsung Electronics Co., Ltd.)
  • US20090026524A1 — Stacked Circuits (Franz Kreupl)
  • US20090200605A1 — Metal-Oxide-Semiconductor Device Including an Energy Filter (Bjoerk Mikael T)
  • US20100067853A1 — Components for optical interconnect through printed wiring boards (Kuznia Charles B)
  • US20100120246A1 — Methods Of Forming Electrically Insulative Materials, Methods Of Forming Low k Dielectric Regions, And Methods Of Forming Semiconductor Constructions (Schrinsky Alex J)
  • US20100123202A1 — Integrated circuit with stacked devices (Qimonda Ag)
  • US20100200949A1 — Method for tuning the threshold voltage of a metal gate and high-k device (International Business Machines Corporation)

Classification

  • G11C5/025primary — Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
  • H01L21/6835primary
  • B82Y10/00 — Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
  • G11C5/06 — Arrangements for interconnecting storage elements electrically, e.g. by wiring
  • G11C8/16 — Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
  • H01L21/743
  • H01L21/76254
  • H01L21/76898
  • H01L2221/68368
  • H01L2223/5442
  • H01L2223/54426
  • H01L2224/131
  • H01L2224/16145
  • H01L2224/16146
  • H01L2224/16227
  • H01L2224/16235
  • H01L2224/32145
  • H01L2224/32225
  • H01L2224/45124
  • H01L2224/45147
  • H01L2224/48091
  • H01L2224/48227
  • H01L2224/73204
  • H01L2224/73253
  • H01L2224/73265
  • H01L2224/81005
  • H01L2224/83894
  • H01L2225/06513
  • H01L2225/06541
  • H01L23/3677
  • H01L23/481
  • H01L23/5252
  • H01L24/13
  • H01L24/16
  • H01L24/45
  • H01L24/48
  • H01L25/0655
  • H01L25/0657
  • H01L25/50
  • H01L2924/00011
  • H01L2924/01002
  • H01L2924/01004
  • H01L2924/01013
  • H01L2924/01018
  • H01L2924/01019
  • H01L2924/01029
  • H01L2924/01046
  • H01L2924/01066
  • H01L2924/01068
  • H01L2924/01077
  • H01L2924/01078
  • H01L2924/01322
  • H01L2924/10253
  • H01L2924/10329
  • H01L2924/12032
  • H01L2924/12033
  • H01L2924/12036
  • H01L2924/12042
  • H01L2924/1301
  • H01L2924/1305
  • H01L2924/13062
  • H01L2924/13091
  • H01L2924/14
  • H01L2924/1461
  • H01L2924/15311
  • H01L2924/1579
  • H01L2924/16152
  • H01L2924/181
  • H01L2924/19041
  • H01L2924/30105
  • H01L2924/3011
  • H01L2924/3025
  • H10B10/00 — Static random access memory [SRAM] devices
  • H10B10/125 — Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
  • H10B10/18 — Peripheral circuit regions
  • H10B12/05 — Making the transistor
  • H10B12/053 — Making the transistor the transistor being at least partially in a trench in the substrate
  • H10B12/09 — Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
  • H10B12/20 — DRAM devices comprising floating-body transistors, e.g. floating-body cells
  • H10B12/50 — Peripheral circuit region structures
  • H10B20/00 — Read-only memory [ROM] devices
  • H10B20/20 — Programmable ROM [PROM] devices comprising field-effect components
  • H10B20/25 — One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
  • H10B41/20 — Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
  • H10B41/40 — Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B41/41 — Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
  • H10B43/20 — EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
  • H10B43/40 — EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H10D10/051 — Manufacture or treatment of vertical BJTs
  • H10D30/014 — Manufacture or treatment of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors
  • H10D30/0411 — Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
  • H10D30/0413 — Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having charge-trapping gate insulators, e.g. MNOS transistors
  • H10D30/0512 — Manufacture or treatment of FETs having PN junction gates of FETs having PN homojunction gates
  • H10D30/43 — FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
  • H10D30/60 — Insulated-gate field-effect transistors [IGFET]
  • H10D30/62 — Fin field-effect transistors [FinFET]
  • H10D30/6728 — Vertical TFTs
  • H10D30/6744 — Monocrystalline silicon
  • H10D30/681 — Floating-gate IGFETs having only two programming levels
  • H10D30/69 — IGFETs having charge trapping gate insulators, e.g. MNOS transistors
  • H10D30/711 — Insulated-gate field-effect transistors [IGFET] having floating bodies
  • H10D30/792 — Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
  • H10D62/121 — Nanowire, nanosheet or nanotube semiconductor bodies oriented parallel to substrates
  • H10D64/027 — Manufacture or treatment forming recessed gates, e.g. by using local oxidation by etching at gate locations
  • H10D64/513 — Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
  • H10D84/0142 — Manufacturing their gate conductors the gate conductors having different shapes or dimensions
  • H10D84/0172 — Manufacturing their gate conductors
  • H10D84/0186 — Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
  • H10D84/0195 — Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices the components including vertical IGFETs
  • H10D84/038 — Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
  • H10D84/83 — Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
  • H10D84/8311 — Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] the IGFETs characterised by having different channel structures
  • H10D84/83138 — Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] the IGFETs characterised by having different shapes or dimensions of their gate conductors
  • H10D84/837 — Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising vertical IGFETs
  • H10D84/85 — Complementary IGFETs, e.g. CMOS
  • H10D84/907 — CMOS gate arrays
  • H10D84/998 — Input and output buffer/driver structures
  • H10D86/01 — Manufacture or treatment
  • H10D86/0214 — Manufacture or treatment of multiple TFTs using temporary substrates
  • H10D86/201 — Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
  • H10D86/40 — Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
  • H10D86/60 — Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
  • H10D87/00 — Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
  • H10D88/00 — Three-dimensional [3D] integrated devices
  • H10D88/01 — Manufacture or treatment
  • H10D89/10 — Integrated device layouts
  • H10P72/74 — Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
  • H10P72/7416 — Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
  • H10P72/7434 — Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
  • H10P90/1916 — Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
  • H10W10/181 — Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
  • H10W20/021 — Manufacture or treatment of interconnections within wafers or substrates
  • H10W20/023 — Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
  • H10W20/20 — Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
  • H10W20/491 — Antifuses, i.e. interconnections changeable from non-conductive to conductive
  • H10W40/10 — Arrangements for heating
  • H10W40/228 — Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area the projecting parts being wire-shaped or pin-shaped
  • H10W46/00 — Marks applied to devices, e.g. for alignment or identification
  • H10W46/101 — Marks applied to devices, e.g. for alignment or identification characterised by the type of information, e.g. logos or symbols
  • H10W46/301 — Marks applied to devices, e.g. for alignment or identification for alignment
  • H10W46/501 — Marks applied to devices, e.g. for alignment or identification for use before dicing
  • H10W72/07207 — Temporary substrates, e.g. removable substrates
  • H10W72/07331 — Connecting techniques
  • H10W72/20 — Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/252 — Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
  • H10W72/50 — Bond wires
  • H10W72/5524 — Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
  • H10W72/5525 — Materials of bond wires comprising metals or metalloids, e.g. silver comprising copper [Cu]
  • H10W72/877 — Bump connectors and die-attach connectors
  • H10W72/884 — Die-attach connectors and bond wires
  • H10W74/00 — Encapsulations, e.g. protective coatings
  • H10W74/15 — Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
  • H10W90/00 — Package configurations
  • H10W90/26 — Configurations of stacked chips the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
  • H10W90/288 — Configurations of stacked chips characterised by arrangements for thermal management of the stacked chips
  • H10W90/297 — Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
  • H10W90/722 — Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
  • H10W90/724 — Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
  • H10W90/732 — Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
  • H10W90/734 — Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
  • H10W90/752 — Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between stacked chips
  • H10W90/754 — Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Family

  • US12564006B2 — B2 (2026)
  • US20240404866A1 — A1 (2024)

Abstract

A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, which each include a single crystal channel; a first metal layer with an overlaying second metal layer; a second level including second transistors, overlaying the first level; a third level including third transistors, overlaying the second level; a fourth level including fourth transistors, overlaying the third level, where the second level includes first memory cells, where each of the first memory cells includes at least one of the second transistors, where the fourth level includes second memory cells, where each of the second memory cells includes at least one of the fourth transistors, where the first level includes memory control circuits, where second memory cells include at least four memory arrays, each of the four memory arrays are independently controlled, and at least one of the second transistors includes a metal gate.

Also asserted by MonolithIC 3D Inc.

  • US 12,250,830 — 3D semiconductor memory devices and structures (3 defendants)
  • US 12,362,330 — 3D semiconductor device and structure with connection paths (3 defendants)
  • US 12,400,961 — 3D semiconductor device and structure with metal layers (3 defendants)

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