US 12,400,961 3D semiconductor device and structure with metal layers
3 defendants · 3 suits · updated October 6, 2026
Also cited as U.S. Patent No. 12,400,961 · US12400961B2 · US 12,400,961 B2 · 12400961 · the '961 patent
MonolithIC 3D Inc. has filed 3 patent-infringement suits on US 12,400,961, "3D semiconductor device and structure with metal layers" since May 11, 2026, 1 of them in the W.D. Tex., against 3 distinct defendants including NVIDIA Corporation, SK hynix Inc. and MonolithIC 3D Inc.. The patent was granted August 26, 2025 on a priority date of March 12, 2013. Its abstract opens: "A semiconductor device including: a first level including: a first silicon layer including a first single crystal silicon layer; first transistors each including a single-crystal channel; a first metal layer connected to the first transistors and the second…" The examiner cited 4 references during prosecution.
- Assignee
- Monolithic 3D Inc
- Priority date
- March 12, 2013
- Granted
- August 26, 2025
- Expires
- March 12, 2033
- Status
- Active
- Claims
- 20 (3 independent)
- Inventors
- Zvi Or-Bach, Brian Cronquist
- Full text
- Google Patents
The suits
3 cases · W.D. Tex. (1) · E.D. Tex. (1) · N.D. Cal. (1)
| Filed | Defendant | Plaintiff | Court | Docket |
|---|---|---|---|---|
| 2026-05-11 | NVIDIA Corporation | MonolithIC 3D Inc. | W.D. Tex. | 7:26-cv-00190 |
| 2026-05-11 | SK hynix Inc. | MonolithIC 3D Inc. | E.D. Tex. | 2:26-cv-00393 |
| 2026-06-11 | MonolithIC 3D Inc.DJ | Sandisk Corporation | N.D. Cal. | 5:26-cv-05641 |
Docket links open the public record on CourtListener. Filing dates are the complaint's.
Independent claims
What is actually asserted, verbatim.
1. A semiconductor device, the device comprising: a first level comprising: a first silicon layer comprising a first single crystal silicon layer; a plurality of first transistors each comprising a single-crystal channel; a first metal layer connected to said plurality of first transistors; a second metal layer connected to said first metal layer; a third metal layer connected to said second metal layer; a second level comprising a plurality of second transistors, said second level is disposed over said first level; a third level comprising a plurality of third transistors, said third level is disposed over said second level; a fourth metal layer disposed over said third level; a fifth metal layer disposed over said fourth metal layer; and a via disposed through said second level, wherein at least one of said plurality of second transistors comprises a metal gate, wherein said device comprises at least one temperature sensor, and wherein at least one element within at least one of said plurality of second transistors has been processed independently of said plurality of third transistors.
8. A semiconductor device, the device comprising: a first level comprising: a first silicon layer comprising a first single crystal silicon layer; a plurality of first transistors each comprising a single-crystal channel; a first metal layer connected to said plurality of first transistors; a second metal layer connected to said first metal layer; a third metal layer connected to said second metal layer; a second level comprising a plurality of second transistors, said second level is disposed over said first level; a third level comprising a plurality of third transistors, said third level is disposed over said second level; a fourth metal layer disposed over said third level; a fifth metal layer disposed over said fourth metal layer; and a via disposed through said second level, wherein at least one of said plurality of second transistors comprises a metal gate, wherein said device comprises at least one temperature sensor, wherein at least one element within at least one of said plurality of second transistors has been processed independently of said plurality of third transistors, and wherein said first level comprises a plurality of capacitors.
15. A semiconductor device, the device comprising: a first level comprising: a first silicon layer comprising a first single crystal silicon layer; a plurality of first transistors each comprising a single-crystal channel; a first metal layer connected to said plurality of first transistors; a second metal layer connected to said first metal layer; a third metal layer connected to said second metal layer; a second level comprising a plurality of second transistors, said second level is disposed over said first level; a third level comprising a plurality of third transistors, said third level is disposed over said second level; a fourth metal layer disposed over said third level; a fifth metal layer disposed over said fourth metal layer; and a via disposed through said second level, wherein at least one of said plurality of second transistors comprises a metal gate, wherein at least one element within at least one of said plurality of second transistors has been processed independently of said plurality of third transistors, wherein said first level comprises a first data bus, wherein said second level comprises a second data bus, and wherein said first data bus and said second data bus are connected.
Art before the examiner
4 references of record, 4 cited by the examiner.
Everything listed here was before the Office and is what a challenge must go beyond. Art the examiner never saw is where an invalidity search starts.
Examiner-cited
- US20070018313A1 — Electronic parts packaging structure and method of manufacturing the same (Shinko Electric Industries Co., Ltd.)
- US20100193964A1 — method of making 3d integrated circuits and structures formed thereby (International Business Machines Corporation)
- US20120248595A1 — System comprising a semiconductor device and structure (MonolithlC 3D Inc.)
- US20200135697A1 — Power and Temperature Management for Functional Blocks Implemented by a 3D Stacked Integrated Circuit (Micron Technology, Inc.)
Classification
- H01L23/5286primary
- H10P72/74primary — Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
- H10W20/427primary — Power or ground buses
- H01L22/34
- H01L23/5226
- H01L23/5283
- H10B80/00 — Assemblies of multiple devices comprising at least one memory device covered by this subclass
- H10D84/0149 — Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
- H10D84/0177 — Manufacturing their gate conductors the gate conductors having different materials or different implants
- H10D84/0186 — Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
- H10D84/038 — Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
- H10D84/83 — Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85 — Complementary IGFETs, e.g. CMOS
- H10D84/856 — Complementary IGFETs, e.g. CMOS the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS
- H10D86/011 — Manufacture or treatment comprising FinFETs
- H10D86/215 — Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI comprising FinFETs
- H10D88/00 — Three-dimensional [3D] integrated devices
- H10D88/01 — Manufacture or treatment
- H10D88/101 — Three-dimensional [3D] integrated devices comprising components on opposite major surfaces of semiconductor substrates
- H10D89/601 — Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
- H10D89/811 — Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
- H10P72/7426 — Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
- H10P72/7438 — Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
- H10P74/277 — Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers
- H10P90/1916 — Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
- H10W10/181 — Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
- H10W20/42 — Vias, e.g. via plugs
- H10W20/435 — Cross-sectional shapes or dispositions of interconnections
- H10W40/228 — Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area the projecting parts being wire-shaped or pin-shaped
- H10W70/658 — Shapes or dispositions of interconnections for devices provided for in groups H10D8/00 - H10D48/00
- H10W90/00 — Package configurations
- H10W90/288 — Configurations of stacked chips characterised by arrangements for thermal management of the stacked chips
- H10W90/297 — Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
Family
- US12400961B2 — B2 (2025)
- US20240379553A1 — A1 (2024)
Abstract
A semiconductor device including: a first level including: a first silicon layer including a first single crystal silicon layer; first transistors each including a single-crystal channel; a first metal layer connected to the first transistors and the second metal layer; a third metal layer connected to the second metal layer; a second level including second transistors; a third level including third transistors, the third level is disposed over the second level which is disposed over the first level; a fifth metal layer disposed over a fourth metal layer disposed over the third level; and a via disposed through the second level, where at least one of the second transistors includes a metal gate, where the device includes at least one temperature sensor, and where at least one element within at least one of the second transistors has been processed independently of the third transistors.
Also asserted by MonolithIC 3D Inc.
- US 12,250,830 — 3D semiconductor memory devices and structures (3 defendants)
- US 12,362,330 — 3D semiconductor device and structure with connection paths (3 defendants)
- US 12,564,006 — 3D semiconductor device and structure with memory cells and multiple metal layers (3 defendants)
Named in one of these suits? A prior-art search is commissioned once and serves every defendant who shares it. The examiner's own search record is free on the tools page, and your first preliminary search is free — one claim, back within 24 hours — so you know whether there is art the Office never saw before anyone pays for more. Flat fees: $2,500$899 for the independent claims, $5,000$1,500 for every asserted claim.
This page is assembled from public records — federal court dockets and the patent's own file — and is updated as the case list changes. It states what the record shows and is not an opinion on the validity or infringement of any claim. Patent data via Google Patents; docket data via CourtListener.